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| STK11C68-M STK11C68-M CMOS nvSRAM High Performance 8K x 8 Nonvolatile Static RAM MIL-STD-883/SMD # 5962-92324 FEATURES * * * * * * * * * * * * 35, 45 and 55ns Access Times 17, 20 and 25ns Output Enable Access Unlimited Read and Write to SRAM Software STORE Initiation Automatic STORE Timing 100,000 STORE cycles to EEPROM 10 year data retention in EEPROM Automatic RECALL on Power Up Software RECALL Initiation Unlimited RECALL cycles from EEPROM Single 5V 10% Operation Available in multiple standard packages DESCRIPTION The Simtek STK11C68-M is a fast static RAM (35, 45 and 55ns), with a nonvolatile electrically-erasable PROM (EEPROM) element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in EEPROM. Data transfers from the SRAM to the EEPROM (STORE), or from the EEPROM to the SRAM (RECALL) are initiated through software sequences. It combines the high performance and ease of use of a fast SRAM with nonvolatile data integrity. The STK11C68-M is pin compatible with industry standard SRAMs and is available in a 28-pin 300 mil ceramic DIP or 28-pad LCC package. Commercial and industrial devices are also available. LOGIC BLOCK DIAGRAM EEPROM ARRAY 256 x 256 A3 A4 ROW DECODER PIN CONFIGURATIONS A7 A 12 Vcc NC W NC NC A8 A9 A11 G A 10 E DQ 7 DQ 6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 3 2 A6 A5 A4 A3 A2 A1 A0 A0 A 12 4 5 6 7 8 9 10 11 12 1 28 27 26 25 24 23 A 12 A7 A6 A5 A4 A3 A2 A1 A0 DQ 0 DQ 1 DQ 2 VSS VCC W NC A8 A9 A 11 G A 10 E DQ 7 DQ 6 DQ 5 DQ 4 DQ 3 STORE STATIC RAM ARRAY 256 x 256 RECALL A5 A6 A7 A8 A9 A12 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 TOP VIEW 22 21 20 19 18 DQ 0 DQ 1 13 14 15 16 17 DQ2 Vss DQ3 DQ4 STORE/ RECALL CONTROL 28 - LCC DQ5 28 - 300 C-DIP COLUMN I/O INPUT BUFFERS PIN NAMES A0 - A12 W DQ0 - DQ7 E Address Inputs Write Enable Data In/Out Chip Enable Output Enable Power (+5V) Ground COLUMN DECODER A0 A1 A2 A10 A 11 G G VCC VSS E W 4-31 STK11C68-M ABSOLUTE MAXIMUM RATINGSa Voltage on typical input relative to VSS. . . . . . . . . . . . . -0.6V to 7.0V Voltage on DQ0-7 and G. . . . . . . . . . . . . . . . . . .-0.5V to (VCC+0.5V) Temperature under bias . . . . . . . . . . . . . . . . . . . . . . -55C to 125C Storage temperature. . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1W DC output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mA (One output at a time, one second duration) Note a: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC CHARACTERISTICS SYMBOL ICC b 1 (VCC = 5.0V 10%) MIN MAX 90 85 80 UNITS mA mA mA mA mA mA mA mA A A V V V 0.4 -55 125 V C tAVAV = 35ns tAVAV = 45ns tAVAV = 55ns E (VCC - 0.2V) all others VIN 0.2V or (VCC - 0.2V) 27 23 20 tAVAV = 35ns tAVAV = 45ns tAVAV = 55ns E VIH; all others cycling E (VCC - 0.2V) all others VIN 0.2V or (VCC - 0.2V) 1 5 2.2 VSS-.5 2.4 VCC+.5 0.8 VCC = max VIN = VSS to VCC VCC = max VIN = VSS to VCC All Inputs All Inputs IOUT = -4mA IOUT = 8mA NOTES PARAMETER Average VCC Current ICC d 2 Average VCC Current during STORE cycle Average VCC Current (Standby, Cycling TTL Input Levels) 50 ISB c 1 ISB c 2 Average VCC Current (Standby, Stable CMOS Input Levels) Input Leakage Current (Any Input) Off State Output Leakage Current Input Logic "1" Voltage Input Logic "0" Voltage Output Logic "1" Voltage Output Logic "0" Voltage Operating Temperature 2 IILK IOLK VIH VIL VOH VOL TA Note b: ICC 1 is dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. Note c: Bringing E VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table. Note d: ICC2 is the average current required for the duration of the store cycle (tSTORE) after the sequence (tWC) that initiates the cycle. AC TEST CONDITIONS Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to 3V Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . 5ns Input and Output Timing Reference Levels. . . . . . . . . . . . . . 1.5V Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 Output 5.0V 480 Ohms CAPACITANCEe (TA=25C, f=1.0MHz) SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance MAX 5 7 UNITS pF pF CONDITIONS V = 0 to 3V V = 0 to 3V 255 Ohms 30pF INCLUDING SCOPE AND FIXTURE Note e: These parameters are guaranteed but not tested. Figure 1: AC Output Loading 4-32 STK11C68-M READ CYCLES #1 & #2 SYMBOLS NO. 1 2 3 4 5 6 7 8 9 10 11 11A #1, #2 tELQV tAVAV g (VCC = 5.0V 10%) STK11C68-35M STK11C68-45M MIN MAX 45 45 35 20 5 5 17 0 17 0 35 45 0 45 55 0 20 0 55 65 5 5 20 0 25 45 25 5 5 25 55 55 25 STK11C68-55M MIN MAX 55 UNITS ns ns ns ns ns ns ns ns ns ns ns ns PARAMETER MIN MAX 35 35 Alt. tACS tRC tAA tOE tOH tLZ tHZ tOLZ tOHZ e Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold After Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby Write Recovery Time tAVQVh tGLQV tAXQX tELQX tEHQZi tGLQX tGHQZi tELICCH tPA tPS tWR tEHICCLc,e tWHQV Note c: Bringing E high will not produce standby currents until any nonvolatile cycle in progress has timed out. See MODE SELECTION table. Note e: Parameter guaranteed but not tested. Note g: For READ CYCLE #1 and #2, W must be high for entire cycle. Note h: Device is continuously selected with E low and G low. Note i: Measured 200mV from steady state output voltage. READ CYCLE #1 g,h 2 tAVAV ADDRESS 5 tAXQX DQ (Data Out) 3 tAVQV DATA VALID W 11A tWHQV READ CYCLE #2 g 2 tAVAV ADDRESS 1 tELQV 11 tEHICCL 7 tEHQZ 9 tGHQZ DATA VALID E tELQX 4 tGLQV 8 tGLQX 6 G DQ (Data Out) tELICCH ICC ACTIVE STANDBY 10 W 11A tWHQV 4-33 STK11C68-M WRITE CYCLES #1 & #2; G high SYMBOLS NO. 12 13 14 15 16 17 18 19 #1 tAVAV tWLWH tELWH tDVWH tWHDX tAVWH tAVWL tWHAX #2 tAVAV tWLEH tELEH tDVEH tEHDX tAVEH tAVEL tEHAX Alt. tWC tWP tCW tDW tDH tAW tAS tWR Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Set-up to End of Write Data Hold After End of Write Address Set-up to End of Write Address Set-up to Start of Write Address Hold After End of Write PARAMETER STK11C68-35M MIN 35 30 30 18 0 30 0 0 MAX STK11C68-45M MIN 45 35 35 20 0 35 0 0 MAX (VCC = 5.0V 10%) STK11C68-55M MIN 55 45 45 30 0 45 0 0 MAX UNITS ns ns ns ns ns ns ns ns WRITE CYCLES #1 & #2; G low SYMBOLS NO. 12 13 14 15 16 17 18 19 20 21 #1 tAVAV tWLWH tELWH tDVWH tWHDX tAVWH tAVWL tWHAX tWLQZ i,m (VCC = 5.0V 10%) STK11C68-35M STK11C68-45M MIN 45 35 35 30 0 35 0 0 35 5 5 35 5 MAX STK11C68-55M MIN 55 45 45 30 0 45 0 0 35 MAX UNITS ns ns ns ns ns ns ns ns ns ns PARAMETER MIN 45 35 35 30 0 35 0 0 MAX #2 tAVAV tWLEH tELEH tDVEH tEHDX tAVEH tAVEL tEHAX Alt. tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Set-up to End of Write Data Hold After End of Write Address Set-up to End of Write Address Set-up to Start of Write Address Hold After End of Write Write Enable to Output Disable Output Active After End of Write tWHQX Note i: Note k: Note m: Measured + 200mV from steady state output voltage. E or W must be VIH during address transitions. If W is low when E goes low, the outputs remain in the high impedance state. 4-34 STK11C68-M WRITE CYCLE #1: W CONTROLLEDk 12 tAVAV ADDRESS 14 tELWH E 18 17 tAVWH 19 tWHAX tAVWL W 13 tWLWH 15 tDVWH 16 tWHDX DATA IN tWLQZ DATA OUT PREVIOUS DATA DATA VALID 20 21 tWHQX HIGH IMPEDANCE WRITE CYCLE #2: E CONTROLLEDk 12 tAVAV ADDRESS 18 tAVEL E 17 tAVEH W 13 tWLEH 15 tDVEH DATA IN DATA VALID 14 tELEH 19 tEHAX 16 tEHDX DATA OUT HIGH IMPEDANCE 4-35 STK11C68-M NONVOLATILE MEMORY OPERATION MODE SELECTION E H L L L W X H L H A12 - A0(hex) X X X 0000 1555 0AAA 1FFF 10F0 0F0F L H 0000 1555 0AAA 1FFF 10F0 0F0E MODE Not Selected Read SRAM Write SRAM Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL I/O Output High Z Output Data Input Data Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z ICC2 Active POWER Standby Active Active Active n,o n,o n,o n,o n,o n n,o n,o n,o n,o n,o n o NOTES Note n: The six consecutive addresses must be in order listed - (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) for a STORE cycle or (0000, 1555, 0AAA,1FFF, 10F0, 0F0E) for a RECALL cycle. W must be high during all six consecutive cycles. See STORE cycle and RECALL cycle tables and diagrams for further details. Note o: I/O state assumes that G VIL. Initiation and operation of nonvolatile cycles does not depend on the state of G. STORE CYCLE INHIBIT and AUTOMATIC POWER-UP RECALL VCC 5.0V 4.0 t STORE inhibit Automatic RECALL 4-36 STK11C68-M STORE/RECALL CYCLE SYMBOLS NO. 22 23 24 25 26 27 28 #1 tAVAV tELQZp tELQXS tELQXR tAVELNs tELEHNs,t tEHAXNs tSTOREq tRECALLr tAE tEP tEA Alt. tRC PARAMETER STK11C68-35M MIN 35 75 10 20 0 25 0 0 35 0 MAX STK11C68-45M MIN 45 75 10 20 0 45 0 MAX (VCC = 5.0V 10%) STK11C68-55M MIN 55 85 10 20 MAX UNITS ns ns ms s ns ns ns STORE/RECALL Initiation Cycle Time Chip Enable to Output Inactive STORE Cycle Time RECALL Cycle Time Address Set-up to Chip Enable Chip Enable Pulse Width Chip Disable to Address Change Note p: Once the software STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs. Note q: Note that STORE cycles (but not RECALLs) are aborted by VCC < 4.0V (STORE inhibit). Note r: A RECALL cycle is initiated automatically at power up when VCC exceeds 4.0V. tRECALL is measured from the point at which VCC exceeds 4.5V. Note s: Noise on the E pin may trigger multiple read cycles from the same address and abort the address sequence. Note t: If the Chip Enable Pulse Width is less than tELQV (see READ CYCLE #2) but greater than or equal to tELEHN, then the data may not be valid at the end of the low pulse, however the STORE or RECALL will still be initiated. Note u: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW throughout. Addresses #1 through #6 are found in the MODE SELECTION table. Address #6 determines whether the STK11C68-M performs a STORE or RECALL. Note v: E must be used to clock in the address sequence for the Software STORE and RECALL cycles. STORE/RECALL CYCLE u,v 22 tAVAV ADDRESS tAVELN E 24 tSTORE 23 tELQZ DATA OUT DATA VALID DATA VALID HIGH IMPEDANCE ADDRESS #1 22 tAVAV ADDRESS #6 26 tELEHN 27 tEHAXN 28 25 tRECALL 4-37 STK11C68-M DEVICE OPERATION The STK11C68-M has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as an ordinary static RAM. In nonvolatile operation, data is transferred from SRAM to EEPROM or from EEPROM to SRAM. In this mode SRAM functions are disabled. SRAM READ The STK11C68-M performs a READ cycle whenever E and G are LOW while W is HIGH. The address specified on pins A0-12 determines which of the 8192 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ CYCLE #1). If the READ is initiated by E or G, the outputs will be valid at tELQV or at tGLQV, whichever is later (READ CYCLE #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought HIGH or W is brought LOW. The STK11C68-M is a high speed memory and therefore must have a high frequency bypass capacitor of approximately 0.1F connected between DUT VCC and VSS using leads and traces that are as short as possible. As with all high speed CMOS ICs, normal careful routing of power, ground and signals will help prevent noise problems. SRAM WRITE A write cycle is performed whenever E and W are LOW. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W go HIGH at the end of the cycle. The data on pins DQ0-7 will be written into the memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. It is recommended that G be kept HIGH during the entire WRITE cycle to avoid data bus contention on common I/O lines. If G is left LOW, internal circuitry will turn off the output buffers tWLQZ after W goes LOW. NONVOLATILE STORE The STK11C68-M STORE cycle is initiated by executing sequential READ cycles from six specific address locations. By relying on READ cycles only, the STK11C68-M implements nonvolatile operation while remaining pin-for-pin compatible with standard 8Kx8 SRAMs. During the STORE cycle, an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. The program operation copies the SRAM data into nonvolatile elements. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of reads from specific addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted and no STORE or RECALL will take place. To initiate the STORE cycle the following READ sequence must be performed: 1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0000 (hex) 1555 (hex) 0AAA (hex) 1FFF (hex) 10F0 (hex) 0F0F (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE Cycle Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, although it is not necessary that G be LOW for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation. HARDWARE PROTECT The STK11C68-M offers hardware protection against inadvertent STORE cycles through VCC Sense. A STORE cycle will not be initiated, and one in progress will discontinue, if VCC goes below 4.0V. 4.0V is a typical, characterized value. The datasheet specifications are guaranteed only for VCC = 5.0 +10%. NONVOLATILE RECALL A RECALL cycle of the EEPROM data into the SRAM is initiated with a sequence of READ operations in a manner similar to the STORE initiation. To initiate the RECALL cycle the following sequence of READ operations must be performed: 1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0000 (hex) 1555 (hex) 0AAA (hex) 1FFF (hex) 10F0 (hex) 0F0E (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL Cycle 4-38 STK11C68-M Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. On power-up, once VCC exceeds the VCC sense voltage of 4.0V, a RECALL cycle is automatically initiated. The voltage on the VCC pin must not drop below 4.0V once it has risen above it in order for the RECALL to operate properly. Due to this automatic RECALL, SRAM operation cannot commence until tRECALL after VCC exceeds 4.0V. 4.0V is a typical, characterized value. If the STK11C68-M is in a WRITE state at the end of power-up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10K Ohm resistor should be connected between W and system VCC. 4-39 STK11C68-M ORDERING INFORMATION STK11C68 - 5 C 35 M Temperature Range M = Military (-55 to 125 degrees C) Access Time 35 = 35ns 45 = 45ns 55 = 55ns Package C = Ceramic 28 pin 300-mil DIP with gold lead finish K = Ceramic 28 pin 300-mil DIP with solder DIP finish L = Ceramic 28 pin LCC Retention / Endurance 10 years / 100,000 cycles 5962-92324 04 MX X Lead Finish A = Solder DIP lead finish C = Gold lead DIP finish X = lead finish "A" or "C" is acceptable Package MX = Ceramic 28 pin 300-mil DIP MY = Ceramic 28 pin LCC Access Time 04 = 55ns 05 = 45ns 06 = 35ns 4-40 |
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